The function of an integrated circuit package is to provide protection of the circuit, distribute power and signals, and dissipate heat. Rapid advances in semiconductor technology have out paced developments in semiconductor packaging techniques. Specifically, increases in the number of signal and power connections on integrated circuits, larger chip sizes, increased power consumption and higher operating frequencies strain the ability of traditional semiconductor packages to provide reliable, cost-effective performance. While some recent advances in packaging technologies have begun to address some of the needs of higher performance integrated circuits, improved packaging technologies are still needed to allow high I/O count and increased density integrated circuits to perform to levels intended by their designers.
Packaging technologies, such as thin quad flat packs (TQFPs), ball grid arrays (BGAs), tape automated bonding (TAB), ultra-thin packages, bare chips or chip-on-board (COB), flip-chip assemblies and multichip modules (MCMs) are now being developed and improved to address performance issues.
In a BGA, in lieu of package pins, an array of solder balls is located on the bottom of a substrate. BGAs permit higher I/O counts without requiring the fine line printed wiring boards required for peripherally leaded packages. BGA yields are typically higher than those for fine-pitch packages, since they have more space between contacts. Further, BGA packages will withstand some degree of mishandling without damaging the leads, whereas fine lead parts must be handled with care before soldering so that the leads are not bent or broken. Thus, BGAs can provide as good as, if not better cost per pin than QFPs. Other benefits of BGAs are that they provide short trace lengths between the package and the printed circuit board (PCB), which reduces signal inductance, and they have a lower profile and a smaller package than QFPs, which allows for more parts to be placed on a board. The small size also means shorter distances between parts, again reducing signal delays. Moreover, since BGAs have large channels between pads, more signals can be routed on the circuit board.
In addition to electrical requirements, heat dissipation is a key factor in designing a semiconductor package, especially since integrated circuit devices are now often used in areas which have little of no air flow. Typically, heat dissipation has been provided through increased air flow (e.g., via fans) and through the use of cooling systems. Techniques for heat dissipation include liquid-cooling techniques, refrigeration, and immersion. However, these techniques are often expensive and impractical for an IC package. A ceramic package is able to handle higher wattages than a plastic package, but ceramic generally is both more expensive and more fragile than plastic. In order to increase heat dissipation in plastic packages, some packages provide thermal vias and heat spreaders between pads. Since the space between pads in BGAs is relatively large, thermal vias can be placed directly under the chip.
The performance of a package is a function of how many I/O it can provide the integrated circuit, how low the inductance of the signal and power distribution paths, and how well the package removes heat. The cost of a packaging solution is a function of the cost of the package, the assembly process and the cost of preparing the integrated circuit for the type of assembly.
BGA packages have :been constructed using plastic, ceramic, and thin film redistribution on top of plastic and ceramic. In the most common case, an integrated circuit is wire bonded to a plastic or ceramic substrate. The die is face up, with its back side bonded to the substrate. On the opposite side of the substrate are the solder balls. Wire bonds are then run from the top of the die and fanned out to the substrate. If thin film redistribution is used, the number of wire bonds can be greater and the length somewhat short because the fan out is done in the thin film. While the increase in the number of I/O and the reduced wire bond length is beneficial, the wire bonds are still longer than is desirable because the die bonding surface is as high as 25 mils above the substrate. This leads to minimum wire bond length of approximately 50 mils with the distance to power and ground still further due to the path traveled in the thin film to a power/ground via. Additionally, the thermal path is through the substrate with this configuration and is unsatisfactory for high performance integrated circuits. Thermal vias can be added to the substrate to marginally improve the heat transfer, but the heat flow is still limited by the printed wiring board. Using thin film redistribution also adds significant cost to the package.
Plastic packages with heat slugs and ceramic packages have been used with cavities where the die is bonded in the cavity and the package is configured in a cavity down arrangement. To handle medium to high I/O counts in this configuration multiple signal bonding shelves are built into the package. While these packages represent an improvement in thermal performance over the ones above the requirement of multiple bonding rows significantly increase the wire bond length. Lengths of 150 mils are common. This wire length increases the inductance of the signal and power distribution limiting the frequency of operation, the number of I/O that can be switched simultaneously on the integrated circuit, and hence limits the performance of the integrated circuit.
Flip chip die attach has been used with the thin film redistribution packages above greatly improving the number of I/O connections. However, cost for the additional metallurgy on the integrated circuit, lack of infrastructure for integrated circuits or this type of assembly and the requirements for adding a metal lid on the package make this method currently cost prohibitive.
Another drawback of ceramic packages is that the coefficient of thermal expansion (CTE) of ceramic is very different from the CTE of the printed circuit board (PCB), such as a typical FR-4 board. Mismatches in CTE can cause stress on solder joints and wire bonds, resulting in poor reliability.
Semiconductor packages are subjected to high temperatures during processing, testing and soldering. Accordingly, it is important that the package be able to withstand high temperatures without inhibiting or degrading electrical performance. Water or moisture in a package can cause a breakdown in package electrical performance. Thus, care must be exercised during processing to prevent moisture absorption during processing.
It would be desirable to provide an integrated circuit package which allows an integrated circuit to operate at the performance level intended by the circuit designer. It would further be desirable to provide such a package which is both very reliable, easy to handle and is capable of dissipating thermal energy generated by an integrated circuit operating at a high frequency. It would further be desirable to provide a package that does not require the modification of metallurgies or the addition of metal layers to standard semiconductors. It would further be desirable to provide a package that can utilize the existing wire bond assembly infrastructure. It would also be desirable to provide such an integrated circuit package which absorbs less moisture during fabrication.